This page presents and provides links for all publications I was an author or co-author in. Please also refer to my CV for more information such as patents, funding proposals, and others:
Ideal NoC Latency with Pre-Configured Routes". Research paper
published in 1st ACM/IEEE International
Symposium on Networks-on-Chip, 2007. Slides.
Efficient Interprocessor Communication Mechanics". Research
paper published in SAMOS IC 2007.
Buffer Flow Control for On-Chip Networks ". Research paper
published in the 15th
International Symposium on High-Performance Computer Architecture
(HPCA), 2009. Slides.
- "Router Designs for Elastic
Buffer On-Chip Networks". Research paper
published in SC09: Supercomputing
Conference 2009. Slides.
- "Evaluating Bufferless Flow
Control for On-chip Networks". Research paper
published in the 4th ACM/IEEE International
Symposium on Networks-on-Chip, 2010. Slides.
Best paper award candidate.
- "Packet Chaining: Efficient Single-Cycle Allocation for
On-Chip networks". Research paper
in the 44th annual IEEE/ACM International
Symposium on Microarchitecture, 2011. Slides.
- "Adaptive Backpressure: Efficient Buffer Management for
On-Chip Networks”. Research paper
in the 30th
IEEE International Conference On Computer Design, 2012.
- "Network Congestion Avoidance through Speculative
Reservation”. Research paper
in the 18th
International Symposium on High Performance Computer Architecture,
- "A Detailed
and Flexible Cycle-Accurate Network-on-Chip Simulator". Research paper
published in the 13th IEEE International
Symposium on Performance Analysis of Systems and Software, 2013.
- "Extending Summation Precision for Network Reduction
Operations”. Research paper
published in the 25th IEEE International Symposium on
Computer Architecture and High Performance Computing, 2013.
- "Channel Reservation Protocol for Over-Subscribed Channels and
Destinations”. Research paper
published in SC13: Supercomputing
- "Variable-Width Datapath for On-Chip Network Static Power
Reduction”. Research paper
published in NOCS14: International Symposium on Networks-on-Chip
- "Collective Memory Transfers for Multi-Core
Chips”. Research paper
published in ICS14: International Conference on Supercomputing
- "OpenSoC Fabric: On-Chip Network Generator,”. Research paper
published in ISPASS16: International Symposium on Performance Analysis of Systems and Software
- "TiDA: High-Level Programming Abstractions for Data Locality Management”. Research paper
published in ISC16: International Supercomputing Conference
- "APHiD: Hierarchical Task Placement to Enable a Tapered Fat Tree Topology for Lower Power and Cost in HPC Networks”. Research paper
published in CCGRID17: 17th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing
· Presented "Enabling
Technology for On-Chip Networks" at Stanford computer forum
meeting 2010, 2009, Stanford CIS meeting Fall 2007, Spring 2008, Fall
2008, Spring 2009, Fall 2009, Sprin 2010 and the 2009 ACS
A small set of introductory slides